The present invention relates to the field of electronic circuits, and more particularly, to techniques for dynamically shifting the phase of clock signal by incremental values.
A phase-locked loop (PLL) is a circuit that measures variations in the phase of an input clock signal. A PLL operates by adjusting the phase of a periodic signal generated by an oscillator. The PLL aligns the phase of the oscillator signal with the phase of the input clock signal. Variations in the phase of the oscillator signal track variations in the phase of the input clock signal. When the phase of the oscillator signal and the input signal are perfectly aligned, the two signals are said to be in lock. The output signal of the PLL is generated from the oscillator signal.
Certain applications for PLLs and DLLs would benefit from being able to dynamically change the phase of a clock signal. For example, some applications would benefit from being able to dynamically increase or decrease the delay of a clock signal. Sampling circuits would benefit from being able to dynamically sweep the phase of the clock signal to locate optimal sampling points. Fractional frequency dividers would also benefit from being able to shift the phase of the clock signal dynamically. Many of these applications require that the circuitry remain ON while the phase of the clock signal is shifted.
Therefore, it would be desirable to provide circuitry that allows the phase of an clock signal to be shifted dynamically, while the circuitry is ON. It would also be desirable to provide dynamic phase shift selection circuitry for clock signals generated by PLL and DLL circuits.